Papers with HDLs
VerilogLAVD: LLM-Aided Pattern Generation for Verilog CWE Detection (2026.acl-long)
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| Challenge: | Existing static analysis tools focus on functional correctness and depend heavily on manual rules. |
| Approach: | They propose a framework that generates executable Traversal Detection Patterns (TDPs) to help detect hardware vulnerabilities. |
| Outcome: | The proposed framework improves the F1 score by 133% compared to LLM-based methods. |